Integrated circuits today rely on extensive re-use of pre-characterized IP bocks and macro cells to meet the demand for high performance system on chip (SoC). In CALVERIFY, we propose a methodology for characterization of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in devices and interconnects. Increasing variability of the process parameters in sub-nanometer designs requires instance-specific characterization of these design blocks. We propose a technique for instance- specific calibration of pre-characterized timing model. The proposed approach was evaluated on large industrial designs of 1.2 M and 3.5 M gates in 90 nm, N28, N16, N14, N7, N5, N3P, N2 and N2P technology and validated against SPICE for accuracy for tier one foundry like TSMC, SMIC, Vanguard and UMC.
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