NLDM Driver Model

NLDM driver model characterizes input-to-output delay and output transition times with sensitivity to input transition time, output load and side input states. These characteristics are obtained using a circuit simulator with appropriate stimulus to cause output transition. Input stimulus along with input/output measurement/capture points are shown in the picture below.

 

NLDM Receiver Model

NLDM receiver model is simply a single capacitor for the entire transition with no sensitivity.

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Shortcomings of NLDM model

NLDM only captures 3 output points, which is not sufficient to reflect non-linearities of circuits at lower geometries (65nm and below) in synthesized driver model during static timing analysis. Classical case of this insufficiency is when driver resistance is order of magnitude less than the impedance of net it is driving (Rd << Znet). Driver model requires more granularity in driver model. CCS timing model eliminate need for this synthesis and hence is able to achieve higher accuracy than NLDM.

Other significant shortcoming of NLDM is in the receiver model. NLDM receiver model fails capture miller effect. This effects dominates delay calculation of STA for very small impedance nets.

 

SoC implementation

The SoC implementation flow requires a .lib file containing electrical information as follows

• Pin capacitance on input pins

• Setup and hold for input pins constrained by a clock

  • Includes data for pin and clock slews

• Delay and retain from clock to output pins

  • Includes data for clock slews and output loads

• Hidden power (power consumed when input switching doesn’t cause the output to switch)

• Leakage

• Noise (immunity on inputs, holding strength on outputs)