CALVERIFY Solutions
for Your Company
CALVERIFY has been delivering services of DKs, design Kits, depending on 0.18um to N2P technology at TSMC, SMIC, SAMSUNG, UMC, Intel and Global Foundry base. CALVERIFY DKs flow, Design Kits, resolves the challenges of beck-end verification of multi-thousand IP combination and time to market requirements. In addition to NLDM, CCS, CCSN, CCSP, ECSM, ECSMN, ECSMNP, Verilog, Verilog-A and UVM format for user requirements, development of customized characterization flow and advanced verification flow has been proven in lots of customers’ first silicon successes at deep submicron technology. On the other hand, CALVERIFY also delivers comprehensive design-for-testability (DFT) services including scan insertion, boundary scan, memory BIST with smart BIST grouping, memory repair solution, scan re-ordering, low power test pattern generation and compression, fault simulation services.
Besides DKs, Design Kits, IP testing and pattern verified has successfully proven on pre-silicon verification.
All above solutions are integrated and embedded on robust workflow management (WFM) system to achieve uncompromising design quality and excellent efficiency.
NLDM model
A NLDM, Non-Linear Delay Model, consists of driver model, net model and a receiver model. Driver model and receiver models are typically characterized using a circuit simulator, whereas net model is either estimated (wire-load, manhattan or star topology) or extracted from a layout using technology parameters of metal, via and contact etc.
CCS family, Composite Current Source
Existing driver models can deliver acceptable accuracy when output waveforms are mostly linear and interconnect resistance is low. However, as integrated circuit technology advances to very deep submicron feature size, waveforms can become highly nonlinear and interconnect resistance can become several kilo ohms. At the same time faster circuit speeds require more accurate delay calculation.
UVM Family
Modeling is a way to create a virtual representation of a real-world system that includes software and hardware. If the software components of this model are driven by mathematical relationships, you can simulate this virtual representation under a wide range of conditions to see how it behaves.
ECSM family, Effective Current Source Model
The ECSM driver model is particularly good at predicting the effect of non-linear waveforms on high impedance interconnects. The model requires additional cell characterization data as described in the items listed above. ECSM relies on the Liberty existing syntax for descriptions of the additional objects to which it applies. The power grid waveforms and power pin parasitics are required for accurate dynamic power grid analysis.
Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits.
Verilog Family
LVF & OCV Family
Sub-16nm technologies and ultra-low VDD's are already stressing the accuracy that can be achieved with the existing LVF sigma constructs alone. In these environments, distributions can be strongly non-Gaussian - exhibiting both mean-shift and skewness effects.