Synthesis, place-and-route, verification and signoff tools rely on detailed model libraries to accurately represent the timing, noise and power performance of digital and memory designs. The complexity of cell libraries dramatically increases as designs migrate to smaller process nodes. Process variability on these nodes requires fast characterization on hundreds of corners. Furthermore, foundries are constantly updating SPICE models, requiring repeated characterization runs. Low-power SoC design further complicates the characterization process by introducing complex cells such as multi-bit flip-flops, multi-voltage level shifters and retention logic, which must be accurately characterized to ensure effective digital implementation across multiple power domains.

​

Signoff-quality libraries with best correlation between results of pre-silicon and Post-silicon.

CALVERIFY’s precise characterization and modeling capability combined with golden accuracy is critical for producing signoff-quality library models, including timing, power, signal integrity and OCV to ensure best PrimeTime accuracy during static timing and power analysis. This unique platform-level integration of CALVERIFY produces the best correlation between pre-silicon and Post-silicon for advanced technology nodes.

​

Comprehensive solution

CALVERIFY is a comprehensive, unified solution that generates libraries for custom I/Os and complex cells, such as multi-bit flip-flops.

​

High performance with pre-characterization optimization

CALVERIFY increases performance by using innovative pre-characterization optimization and intelligent optimization techniques that reduce the number of simulation runs required during the library characterization phase.

​

Advanced node-ready

CALVERIFY is ready for characterizing and modeling libraries at advanced technology nodes, such as 16nm 14nm and 7nm. It supports generation of the latest FinFET models