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-  5+ years of experience in product validation of EDA software or capable fresh graduates. 
-  Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design
-  Knowledge of C/C++ is required

- 3+ years of experience in product validation of EDA software or capable fresh graduates. 
- Proficient in TCL/Python/Perl/Shell scripts, with good scripting skills

- 3+ years of experience with significant and deep industry experience in designing complex protocols and/or hardware systems.

- Need to be familiar with various Liberty models including NLDM, CCS, LVF. ​

- 3+ years of experience with significant and deep industry experience in designing complex protocols and/or hardware systems.

- Must excel in and demonstrate solid debugging experience/skills.