Senior Application Engineer
This is a Verilog modeling and characterization engineer position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes
JOB QUALIFICATION:
- 3+ years of experience with significant and deep industry experience in designing complex protocols and/or hardware systems.
- MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
- Need to be familiar with various Liberty models including NLDM, CCS, LVF.
- Must excel in and demonstrate solid debugging experience/skills.
JOB DESCRIPTION:
- Write RTL models in Verilog for the different flavors of IOs.
- Build verification plan and verify the design including both behavioral models and transistor level implementation.
- Experience in System Verilog assertions(SVA), Power aware verification and formal verification is necessary.
- Debug issues at IP level and SoC level.
- Prior experience in analog/mixed signal simulations is preferred.
- Understand the I/O circuit architecture and write stimulus for Timing/Power characterization.
- Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected.
- Drive and build automation with any of the scripting languages like Python/Perl/TCL to improve the productivity and quality.
- Responsible for developing new methodologies and flows to support complex designs, driving the design verification reviews, automation and drive productivity & quality.
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