Why is it necessary for macro characterization. The SoC implementation flow requires a .lib file containing electrical information as follows :

• Pin capacitance on input pins

• Setup and hold for input pins constrained by a clock

• Includes data for pin and clock slews

• Delay and retain from clock to output pins

• Includes data for clock slews and output loads

• Hidden power (power consumed when input switching doesn’t cause the output to switch)

• Leakage

• Noise (immunity on inputs, holding strength on outputs)

 

Designs now have many distinct macro instances that need an abstract electrical models to enable the SoC Design flow –> synthesis, Place & Route, STA etc.

 

Macro instances consume much of the on-chip power hence are often subject to voltage scaling invalidating pre-existing models created by a memory compiler.

​

40nm or below requires characterization with True-Spice accuracy to model transistor stress and coupling and support for advanced ECSM/CCS/CCSN/ECSMN/CCSP/ECSMP models

 

There are two parts for characterized application. One is memory characterization the other is mixed-signal of phi application.

 

Memory Characterization

• The customer will possess a memory design that will be used as an IP block within a chipSome memories are purchased from a library vendor (Virage, ARM, TSMC, etc)

• The customer may require more PVTs than is included from the vendor

• The customer may have limited knowledge of the internal workings of the memories

• Others are developed in house

• The customer will have knowledge of the internal workings of the design

• CALVERIFY has successfully characterized a wide range of embedded memory designs, like Single Port SRAM, Dual Port SRAM, Pseudo Dual Port SRAM, ROM, TCAM, CAMRAM and FIFO.

 

Mixed-signal Characterization

• CALVERIFY solution includes “Highly efficient and automated electrical view creation and validation for all IP blocks.”

• Logic (std cells)  and I/O cells, like GPIO, PCI, SSTL, PECL etc.

• Custom digital blocks (custom cells, datapath, cores etc.)

• Interface IP and analog blocks, like USB, Serdes, DDR, PCIe, MIPI, HDMI, DP, etc.

• CALVERIFY has successfully characterized a wide range of analog IP ,like PLL, DAC, ADC, AFE, PVT, OSC and Serdes.

​