The design flow for analog systems is not as clean as is digital system design flow. Analog design flow cannot be automated; practical circuits can’t be automatically synthesized or optimized, mostly due to the fact that analog circuit design must address many more parameters than digital design. Furthermore, analog designs in general are not portable from one technology node to another. A change in technology involves at least device resizing and often requires architecture changes. In addition, once the analog IP is ready to deliver, its successful instantiation into the target circuit is prone to human error. Each bias and reference line requires correct electrical connection. Digital controls, clocks and data must be connected and the timing interface to the analog IP must be correct.

 

Some have claimed that the term “Analog IP” is an oxymoron – that providing analog circuitry in a form which can be plugged in without analysis, and adjustment is simply impossible for other than trivial analog functions.

The position of the article referenced above is that using IP should be as easy as attaching a new printer to your PC. And if the delivered package requires further customization for its end application whether by the vendor or customer, it is not properly IP at all. The vendor is providing a design service.

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Our AMS skills and services

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• Expertise in circuit verification of Mixed-Signal IP’s such as SERDES, PLL, ADC, DAC, Temperature Sensors, Comparator, etc.

• Mixed signal verification

• Post-layout simulations, Silicon validations.

• Develop Automation flows using Tclsh/TK/Shell and Ocean Scripting

• Experience with transistor level simulations; CustomSim, FINESIM, HSPICE, Spectre.

• Experience in Verification of Analog Mixed Signal IPs using System Verilog real number modeling, UVM/OVM.

• Experience in test bench development and writing test cases for Analog and Mixed-Signal verification on UVM platform.

• AMS modelling in Verilog-A/Verilog-AMS & good understanding of the trade-offs between model accuracy and simulation speed.

• Experience using Cadence AMS simulation & schematic tools

• Exposure in FINFET, FDSOI,N2P, N3P, N5, N7, N16, N28, 40nm, 65nm, etc. process technology nodes

 

Project

• SERDES

• PLL

• DAC

• ADC

• Comparator

• Oscillators

• Temperature sensor

• Power Management

• Memory

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Team tasks

• Analog/Mixed Signal Verification for number of SoCs using Fast Spice tools – CustomSim, Finesim, Spectre@XPS.

• AMS models development

• Behavioral & timing models for analog IPs

• Define system level AMS verification test suite, execute sub-system level AMS simulations.