Senior Product Engineer
The Dynamic Model Team (DMT) delivers the industry’s most comprehensive and robust solution for UVM/HDL of customers' foundation IP—from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks.
JOB QUALIFICATION:
- 3+ years of experience with significant and deep industry experience in designing complex protocols and/or hardware systems.
- MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
- Must excel in and demonstrate solid debugging experience/skills.
- Emotionally intelligent collaborator and communicator.
- Experience with team-wide collaboration tools and processes.
- Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive!
JOB DESCRIPTION:
-Verification experience using Cadence simulation and/or emulation products is highly desired.
-Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. Experience in memory sub-system design and operation is strongly recommended.
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